On 5/8/2024 6:24 PM, vallor wrote:
> On 8 May 2024 22:04:40 GMT, rbowman <bowman@montana.com> wrote in
> <la2b7nF8fn1U3@mid.individual.net>:
>
>> On Wed, 8 May 2024 13:07:00 -0400, DFS wrote:
>>
>>> AIDA64 Extreme is even more extreme than HWiNFO.
>>>
>>> https://www.aida64.com/downloads
>>>
>>> https://imgur.com/a/GPWXeyj
>>>
>>> The hardware report alone is 13.5K well-formatted lines, telling you
>>> endless things about your hardware.
>>
>> Is there anything useful in those 13.5K lines?
>
> Maybe not -- but let me tell you, they are "well-formatted"!

It's no laughing matter.

'Well-formatted' = superior = part of the reason HWiNFO (and AIDA64) can
make money from their excellent programs. For example:

CPU flags from HWiNFO (Windows only)

[Standard Feature Flags]
FPU on Chip Present
Enhanced Virtual-86 Mode Present
I/O Breakpoints Present
Page Size Extensions Present
Time Stamp Counter Present
Pentium-style Model Specific Registers Present
Physical Address Extension Present
Machine Check Exception Present
CMPXCHG8B Instruction Present
APIC On Chip / PGE (AMD) Present
Fast System Call Present
Memory Type Range Registers Present
Page Global Feature Present
Machine Check Architecture Present
CMOV Instruction Present
Page Attribute Table Present
36-bit Page Size Extensions Present
Processor Number Not Present
CLFLUSH Instruction Present
Debug Trace and EMON Store Not Present
Internal ACPI Support Not Present
MMX Technology Present
Fast FP Save/Restore (IA MMX-2) Present
Streaming SIMD Extensions Present
Streaming SIMD Extensions 2 Present
Self-Snoop Not Present
Multi-Threading Capable Present
Automatic Clock Control Not Present
IA-64 Processor Not Present
Signal Break on FERR Not Present
Streaming SIMD Extensions 3 Present
PCLMULQDQ Instruction Support Present
MONITOR/MWAIT Support Present
Supplemental Streaming SIMD Extensions 3 Present
FMA Extension Present
CMPXCHG16B Support Present
Streaming SIMD Extensions 4.1 Present
Streaming SIMD Extensions 4.2 Present
x2APIC Not Present
POPCNT Instruction Present
AES Cryptography Support Present
XSAVE/XRSTOR/XSETBV/XGETBV Instructions Present
XGETBV/XSETBV OS Enabled Present
AVX Support Present
Half-Precision Convert (CVT16) Present
[Extended Feature Flags]
FPU on Chip Present
Enhanced Virtual-86 Mode Present
I/O Breakpoints Present
Page Size Extensions Present
Time Stamp Counter Present
AMD-style Model Specific Registers Present
Machine Check Exception Present
CMPXCHG8B Instruction Present
APIC On Chip Present
SYSCALL and SYSRET Instructions Present
Memory Type Range Registers Present
Page Global Feature Present
Machine Check Architecture Present
CMOV Instruction Present
Page Attribute Table Present
36-bit Page Size Extensions Present
Multi-Processing / Brand feature Not Present
No Execute Present
MMX Technology Present
MMX+ Extensions Present
Fast FP Save/Restore Present
Fast FP Save/Restore Optimizations Present
1 GB large page support Present
RDTSCP Instruction Present
x86-64 Long Mode Present
3DNow! Technology Extensions Not Present
3DNow! Technology Not Present
Bit Manipulation Instructions Set 1 Present
Bit Manipulation Instructions Set 2 Present
Advanced Vector Extensions 2 (AVX2) Present
Advanced Vector Extensions 512 (AVX-512) Foundation Not Present
AVX-512 Prefetch Instructions Not Present
AVX-512 Exponential and Reciprocal Instructions Not Present
AVX-512 Conflict Detection Instructions Not Present
AVX-512 Doubleword and Quadword Instructions Not Present
AVX-512 Byte and Word Instructions Not Present
AVX-512 Vector Length Extensions Not Present
AVX-512 52-bit Integer FMA Instructions Not Present
Secure Hash Algorithm (SHA) Extensions Present
Software Guard Extensions (SGX) Support Not Present
Supervisor Mode Execution Protection (SMEP) Present
Supervisor Mode Access Prevention (SMAP) Present
Hardware Lock Elision (HLE) Not Present
Restricted Transactional Memory (RTM) Not Present
Memory Protection Extensions (MPX) Not Present
Read/Write FS/GS Base Instructions Present
Enhanced Performance String Instruction Present
INVPCID Instruction Present
RDSEED Instruction Present
Multi-precision Add Carry Instructions (ADX) Present
PCOMMIT Instructions Not Present
CLFLUSHOPT Instructions Present
CLWB Instructions Present
TSC_THREAD_OFFSET Not Present
Platform Quality of Service Monitoring (PQM) Present
Platform Quality of Service Enforcement (PQE) Present
FPU Data Pointer updated only on x87 Exceptions Not Present
Deprecated FPU CS and FPU DS Not Present
Intel Processor Trace Not Present
PREFETCHWT1 Instruction Not Present
AVX-512 Vector Bit Manipulation Instructions Not Present
AVX-512 Vector Bit Manipulation Instructions 2 Not Present
AVX-512 Galois Fields New Instructions Not Present
AVX-512 Vector AES Present
AVX-512 Vector Neural Network Instructions Not Present
AVX-512 Bit Algorithms Not Present
AVX-512 Carry-Less Multiplication Quadword (VPCLMULQDQ) Present
AVX-512 Vector POPCNT (VPOPCNTD/VPOPCNTQ) Not Present
User-Mode Instruction Prevention Present
Protection Keys for User-mode Pages Not Present
OS Enabled Protection Keys Not Present
Wait and Pause Enhancements (WAITPKG) Not Present
Total Memory Encryption Not Present
Key Locker Not Present
57-bit Linear Addresses, 5-level Paging Not Present
Read Processor ID Present
OS Bus-Lock Detection Not Present
Cache Line Demote Not Present
MOVDIRI: Direct Stores Not Present
MOVDIR64B: Direct Stores Not Present
ENQCMD: Enqueue Stores Not Present
SGX Launch Configuration Not Present
Protection Keys for Supervisor-Mode Pages Not Present
Control-Flow Enforcement Technology (CET) Shadow Stack Present
Attestation Services for Intel SGX Not Present
AVX-512 4 x Vector Neural Network Instructions Word Variable
Precision Not Present
AVX-512 4 x Fused Multiply Accumulation Packed Single Precision Not
Present
Fast Short REP MOV Present
User Interrupts Not Present
AVX-512 VP2INTERSECT Support Not Present
AVX-512 FP16 Not Present
MD_CLEAR Support Not Present
IA32_MCU_OPT_CTRL MSR Support Not Present
Restricted Transactional Memory (RTM) Always Abort Not Present
Restricted Transactional Memory (RTM) Force Abort Not Present
SERIALIZE Not Present
Hybrid Processor Not Present
TSX Suspend Load Address Tracking Not Present
Platform Configuration (PCONFIG) Not Present
Architectural LBRs Not Present
Indirect Branch Restricted Speculation (IBRS), Indirect Branch
Predictor Barrier (IBPB) Not Present
Single Thread Indirect Branch Predictors (STIBP) Not Present
L1D_FLUSH Support Not Present
IA32_ARCH_CAPABILITIES MSR Not Present
IA32_CORE_CAPABILITIES MSR Not Present
Speculative Store Bypass Disable (SSBD) Not Present
Control-Flow Enforcement Technology (CET) Indirect Branch Tracking
Not Present
Advanced Matrix Extensions (AMX) Tile Architecture Not Present
Advanced Matrix Extensions (AMX) bfloat16 Support Not Present
Advanced Matrix Extensions (AMX) 8-bit Integer Operations Not Present
SHA512 Instructions Not Present
SM3 Instructions Not Present
SM4 Instructions Not Present
Advanced Matrix Extensions (AMX) FP16 Instructions Not Present
AVX (VEX-encoded) Vector Neural Network Instructions Not Present
AVX-512 BFLOAT16 Instructions Not Present
Fast Zero-Length MOVSB Not Present
Fast Short STOSB Not Present
Fast Short CMPSB, SCASB Not Present
History Reset Not Present
Linear Address Masking Not Present
Linear Address Space Separation Not Present
RAO-INT Instructions Not Present
CMPccXADD Instructions Not Present
Flexible Return and Event Delivery (FRED) Not Present
LKGS Instruction Not Present
WRMSRNS Instruction Not Present
NMI-source Reporting Not Present
AVX-IFMA Instructions Not Present
RD/WR MSRLIST Instructions Not Present
INVD Execution Prevention After BIOS-Done Not Present
Protected Processor Inventory Number (IA32_PPIN) Support Not Present
PBNDKB Instruction Not Present
AVX-VNNI-INT8 Instructions Not Present
AVX-VNNI-INT16 Instructions Not Present
AVX-NE-CONVERT Instructions Not Present
PREFETCHIT0/1 Instructions Not Present
URDMSR/UWRMSR Instructions Not Present
AMX-COMPLEX Instructions Not Present
CET Supervisor Shadow-Stack Not Present
UIRET Support Not Present
Advanced Vector Extensions 10 (AVX10) Not Present
Advanced Performance Extensions (APX) Foundation Not Present
Not Exhibiting MXCSR Configuration Dependent Timing (MCDT) Not Present
UC-Lock Disable Feature Not Present
LAHF/SAHF Long Mode Support Present
Core Multi-Processing Legacy Mode Present
Secure Virtual Machine Not Present
Extended APIC Register Space Not Present
LOCK MOV CR0 Support Present
Advanced Bit Manipulation Present
SSE4A Support Present
Misaligned SSE Mode Present
PREFETCH(W) Support Present
OS Visible Work-around Support Present
Instruction Based Sampling Not Present
XOP Instruction Support Not Present
SKINIT, STGI, and DEV Support Not Present
Watchdog Timer Support Present
TBM0 Instruction Support Not Present
Lightweight Profiling Support Not Present
FMA4 Instruction Support Not Present
Translation Cache Extension Not Present
NodeId Support Not Present
Trailing Bit Manipulation Not Present
Topology Extensions Present
Core Performance Counter Extensions Present
NB Performance Counter Extensions Not Present
Streaming Performance Monitor Architecture Not Present
Data Breakpoint Extension Not Present
Performance Time-Stamp Counter Not Present
L2I Performance Counter Extensions Not Present
MWAITX/MONITORX Support Present
Secure Memory Encryption Present
Secure Encrypted Virtualization Present
[Enhanced Features]
Core Performance Boost Supported, Enabled

CPU flags from Linux hwinfo command

flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt
pdpe1gb rdtscp lm constant_tsc rep_good nopl tsc_reliable nonstop_tsc
cpuid extd_apicid pni pclmulqdq ssse3 fma cx16 sse4_1 sse4_2 movbe
popcnt aes xsave avx f16c rdrand hypervisor lahf_lm cmp_legacy svm
cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw topoext perfctr_core
ssbd ibrs ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 erms invpcid
rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves
clzero xsaveerptr arat npt nrip_save tsc_scale vmcb_clean flushbyasid
decodeassists pausefilter pfthreshold v_vmsave_vmload umip vaes
vpclmulqdq rdpid fsrm

Who would EVER pay a cent for that low-effort hobbyist output?